A processing circuit may have one or more power saving states for use when the processing hardware is inactive. One example of such a low power state can be provided by the use of a power gating transistor connected in series with the processing circuit. The power gating transistor turns the power supply to the processing circuit on or off. When the power gating transistor is on then the full supply voltage is provided to the processing circuit, while when the power gating transistor is switched off then the power supply is shut off from the processing circuit and any state in the processing circuit is lost.
Another power saving scheme may be provided by a retention switch for supplying the processing circuit with a retention voltage which is different to the supply voltage and results in lower current leakage in the processing circuit but is nevertheless sufficient for the processing circuit to maintain state in its flip flops and latches.
In previously known apparatuses, a processing circuit may be provided with a power gating switch and a retention switch separate from the power gating switch. The power gating switch may be used to switch on and off the power supply to the processing circuit, while the retention switch may be used to supply a retention voltage to the processing circuit. Typically a processing circuit requires many thousands of such switches and so the power gating and retention switches occupy a large proportion of the circuit area of the apparatus. For example, the switches may occupy between 10 and 30% of the entire area of the chip. Moreover, the power switches contribute to a significant amount of static leakage. The present invention seeks to reduce the overhead associated with providing different power saving modes.